Code Generation for Data Processing
Contents
Code generation is a key technique for efficient program execution and data processing. This lecture will cover the following topics from a practical perspective with accompanying hands-on exercises:
- Execution models of programs (interpretation, bytecode, machine code generation, etc.)
- Program representations (source code, intermediate representations (IRs), different forms of bytecode)
- Classical techniques of code generation
- SSA and optimization techniques, exemplary described on LLVM-IR
- Machine code generation: instruction selection and register allocation
- Execution of programs in virtual machines (e.g., WebAssembly, BPF, JavaScript)
- Sandboxing and optimizations for JIT compilation
- Execution of database queries (e.g., SQL, data frame API)
- Execution models and code representations
- Execution of machine code/binary translation (e.g., RISC-V)
- Specifics when translating machine code
Organization
- Lecture with integrated exercises: Thu 10–14 (c.t., with break) in 02.11.018
- Exercises will include hands-on programming tasks
- Language: English
- Module: CIT3230001, 6 ECTS, Bachelor/Master elective
- Area "Databases and Information Systems" for Informatics, Wirtschaftsinformatik/Information Systems, Informatics: Games Engineering, Biomedical Engineering
- B1.2 "Advanced Topics in Data Engineering" for Data Engineering and Analystics
- Written exam (90 minutes), might change to oral on low registration count. Last year's exam: [exam2223.pdf].
- Zulip stream for this lecture; private contact via e-mail
Prerequisites
The course is aimed at bachelor/master students who have taken the following (or similar) courses:
- IN0004 Introduction to Computer Architecture
- IN0008 Fundamentals of Databases
Material
Material and exercises will be regularly provided throughout the semester. [lec.pdf] [prs.pdf]
Note: The schedule below is preliminary and is likely to change during the semester.
| Date | Lecture Topic | Homework |
|---|---|---|
| 19.10. | Overview, Motivation, Interpretation Techniques [lec01.pdf]
Exercise: (no exercise session) | [hw1.txt] [hw1-sol.c] |
| 26.10. | Compiler Front-end [lec02.pdf]
Exercise: discussion of hw1 | [hw2.txt] [hw2-sol.cc] |
| 02.11. | IR Concepts, Control Flow Graph, SSA Construction [lec03.pdf] [prs03.pdf]
Exercise: exercise on IR design [ex03.txt] | (none) |
| 09.11. | LLVM-IR and IR Design Considerations [lec04.pdf]
Exercise: discussion of hw2 and LLVM hands-on [ex04.txt] | [hw3.txt] [hw3-sol.cc] |
| 16.11. | Analyses and Transformations [lec05.pdf] [prs05.pdf]
Exercise: writing an LLVM-IR pass [ex05.txt] | (none) d |
| 23.11. | Vectorization [lec06.pdf]
Exercise: auto-vectorization hands-on [ex06.txt] | (none) |
| 30.11. | Instruction Selection [lec07.pdf] [prs07.pdf]
Exercise: discussion of hw3 | [hw4.txt] [hw4-sol.cc] [rt-aarch64.c] |
| 07.12. | (no lecture/exercise, Dies Academicus) | |
| 14.12. | (no lecture/exercise, lecturer absent) | |
| 21.12. | Query Compilation [lec13.pdf] (slide numbers subject to change)
Exercise: SQLite hands-on [ex13.txt] | (none) |
| 11.01. | Register Allocation [lec08.pdf] [prs08.pdf]
Exercise: discussion of hw4 and SSA destruction [ex08.txt] | [hw5.txt] |
| 18.01. | Object Files, Linker, Loader [lec09.pdf]
Exercise: ELF file construction [ex09.txt] | (none) |
| 25.01. | Unwinding and Debuginfo [lec10.pdf]
Exercise: discussion of hw5 and unwind info generation [ex10.txt] | [hw6.txt] |
| 01.02. | JIT-compilation and Sandboxing [lec11.pdf]
Exercise: WebAssembly hands-on [ex11.txt] | (none) |
| 08.02. | Binary translation [lec12.pdf]
Exercise: discussion of hw6, QEMU hands-on, wrap up [ex12.txt] |